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英國(guó)Ossila晶片S403 OFET測(cè)試晶片S411

英國(guó)Ossila晶片S403 OFET測(cè)試晶片S411
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Specifications

英國(guó)Ossila晶片S403  OFET測(cè)試晶片S411

Applications

Ossila High Density Substrates feature 20 OFETs which can benefit your research in a number of ways. Firstly, production cost is reduced as a result of a higher volume of OFETs per substrate compared to the low density equivalents. This can help to stretch your budget to allow you to produce and test larger numbers of OFETs.

Secondly, producing OFETs is a far faster and less laborious process. Fabrication time is reduced by up to 50% when using prefabricated high density OFETs, freeing up more time to test the devices. As a result of this, greater volumes of statistics can be produced which in turn can provide more robust and reliable research.

英國(guó)Ossila晶片S403  OFET測(cè)試晶片S411

Furthermore, OFET variability is reduced since a larger number of OFETs are produced with each fabrication. At Ossila we have optimised the fabrication process in order to produce consistently high quality substrates. In this respect, using our prefabricated substrates rather than fabricating your own can help you to gather more reliable data to benefit your research project.

Prefabricated high density substrates are ideal for mobility testing as they enable swift, efficient testing of high volumes of OFETs. The Ossila high-density OFET test board has been designed for this purpose.

Rather than using a mechanical probe station to test OFETs, which is a delicate and time-consuming process, the high density test board allows testing of multiple OFETs at one time; simply drop the substrate into the test slot, secure the push-fit lid and connect the board via its BNC connectors to an array of test equipment.

英國(guó)Ossila晶片S403  OFET測(cè)試晶片S411

The board has been inligently designed to reduce external noise, leakage current and stray capacitance in order to provide reliable and precise low-current testing.

The Ossila High Density OFET Test Board, designed for rapid, reliable testing of multiple OFETs.

Specifications

We fabricate p-doped silicon substrates with an insulating 300 nm silicon oxide top layer. Platinum is deposited on top to produce gate electrodes which also cover the conductive edge of the substrate. It is therefore essential that the edge of the substrate is conductive and not covered with the silicon oxide layer. If not, the silicon oxide must be scratched off the sides of the substrates before it can be used.

Structure of our prefabricated silicon/silicon oxide substrates.

At Ossila we have optimised the fabricating process to ensure that the edges are conductive and the substrate immediay ready to use.

We fabricate our high-density substrates with 5 nm of titanium and 100 nm of platinum.

For individual details and dimension drawings of each substrate type see below.

Linear 1 mm x 2 µm variable channel length substrate (S403)

Dimension drawing of 1 mm x 2 µm substrate.

Interdigitated 22.6 mm x 5 µm constant channel length substrate (S411)

Dimension drawing of one of the 22.6 mm x 5 µm devices on the high density substrate.